Lakshmi Mandyam, VP automotive, embedded and automotive business line, Arm, discusses the elevation in automotive processing needs
In my role as Arm’s automotive lead, my team and I are constantly talking with both car makers and our automotive ecosystem discussing progress toward fully-autonomous driving. We of course talk about how we can address their performance, power and security requirements, but most of the discussions focus on safety.
Safety is the highest priority for car makers, for both the obvious technology factors associated with autonomous systems controlling all aspects of driving, but also to ensure that human passengers can trust their automated driver. If consumers don’t trust the autonomous systems in their cars are safe, then mass-market acceptance of this technology will be slow to happen.
Ironically, it’s a human factor, driver error, that autonomous driving is expected to eliminate. Considering 94% of all accidents are a result of driver error, fully autonomous driving is expected to significantly reduce the number of accidents and fatalities. It is why safety cannot be an afterthought and take a backseat to performance, power-efficiency and security when developing autonomous-class SoCs and systems.
Unfortunately, the path to Level 5 autonomy has been paved with prototypes, often based on power-hungry, expensive data center CPUs lacking even the most basic functional safety features.
Arm has prioritized safety for years now. Our automotive ecosystem has access to the industry’s broadest array of functional safety IP with the latest ISO certifications. To further ensure our silicon partners get a head-start on safety, we’ve introduced the Arm Safety Ready program, which centralizes Arm’s massive investment in safety, enabling our silicon partners and the entire automotive supply chain to accelerate their timelines for bringing safer products to market faster.
But our safety leadership doesn’t stop with integrating the latest certifications and standards. We’ve also launched the first autonomous-class processor with integrated safety, the Cortex-A76AE, which has been uniquely designed for automotive and includes split-lock technology, a game-changing safety innovation available for the first time in application processors.
Getting ‘safety ready’ for the next levels of autonomy
The Safety Ready program encompasses Arm’s existing safe and new or future products that have been through a rigorous functional safety process, including systematic flows and development in support of ISO 26262 and IEC 61508 standards. Safety Ready is a one-stop shop for software, tools, components, certifications and standards, aimed at simplifying and reducing the cost of integrating functional safety for Arm partners. By taking advantage of the program offerings, partners and car makers can be confident their SoCs and systems incorporate the highest levels of functional safety required for autonomous applications.
The Cortex-A76AE is uniquely designed for automotive and optimized for 7nm process nodes. AE stands for ‘automotive enhanced’ and any Arm IP with the AE designator will include specific features addressing the requirements of in-vehicle processing.
A high level of processing capability is required for autonomous driving, with inherent safety as standard. Cortex-A76AE delivers both without compromise as a high-performance application processor with split-lock capability.
Car makers can design their autonomous systems to require watts and not the kilowatts required for today prototypes thanks to the Cortex-A76AE. Lower-power also enables a more energy-efficient use of vehicle battery power combined with thermal efficiency to aid the packaging of compute capability while extending the range of vehicles for a lower total cost of driving.
Arm has also introduced AE system IP for designing a comprehensive autonomous-class SoC. The new CoreLink GIC-600AE, CoreLink MMU-600AE and CoreLink CMN-600AE provide critical elements such as high-performance interrupt management, extended virtualization and memory management, and connectivity to multiple CPU clusters to scale performance in safe multicore systems.
